In computer storage devices, such as optical and magnetic disk drives, sampled amplitude read channels employing partial response (PR) signaling with maximum likelihood (ML) sequence detection have provided a substantial increase in storage capacity by allowing for significantly higher linear bit densities. Partial response signaling refers to a particular method for transmitting symbols represented as analog pulses through a communication medium. The benefit is that at the signaling instances (baud rate) there is no intersymbol interference (ISI) from other pulses except for a controlled amount from immediately adjacent, overlapping pulses. Allowing the pulses to overlap in a controlled manner leads to an increase in the symbol rate (linear recording density) without sacrificing performance in terms of signal-to-noise ratio (SNR).
Partial response channels are characterized by the polynomials EQU (1-D)(1+D).sup.n
where D represents a delay of one symbol period and n is an integer. For n=1,2,3, the partial response channels are referred to as PR4, EPR4 and EEPR4, respectively, where the frequency responses for the PR4 and EEPR4 channels are shown in FIG. 1A. The channel's dipulse response, the response to an isolated symbol, characterizes the transfer function of the system (the output for a given input). With a binary "1" bit modulating a positive dipulse response and a binary "0" bit modulating a negative dipulse response, the output of the channel is a linear combination of time shifted dipulse responses. The dipulse response for a PR4 channel (1-D.sup.2) is shown as a solid line in FIG. 1B. Notice that at the symbol instances (baud rate), the dipulse response is zero except at times t=0 and t=2. Thus, the linear combination of time shifted PR4 dipulse responses will result in zero ISI at the symbol instances except where immediately adjacent pulses overlap.
It should be apparent that the linear combination of time delayed PR4 dipulse responses will result in a channel output of +2, 0, or -2 at the symbol instances depending on the binary input sequence. The output of the channel can therefore be characterized as a state machine driven by the binary input sequence and, conversely, the input sequence can be estimated or demodulated by running the signal samples at the output of the channel through an "inverse" state machine. Because noise will obfuscate the signal samples, the inverse state machine is actually implemented as a trellis sequence detector which computes a most likely input sequence associated with the signal samples.
Operation of a PR4 trellis sequence detector is understood from its state transition diagram shown in FIG. 2A. Each state 100 is represented by the last two input symbols (in NRZ after preceding), and each branch from one state to another is labeled with the current input symbol in NRZ 102 and the corresponding sample value 104 it will produce during readback. The demodulation process of the PR4 sequence detector is understood by representing the state transition diagram of FIG. 2A as a trellis diagram shown in FIG. 2B. The trellis diagram represents a time sequence of sample values and the possible recorded input sequences that could have produced the sample sequence. For each possible input sequence, an error metric is computed relative to a difference between the sequence of expected sample values that would have been generated in a noiseless system and the actual sample values output by the channel. For instance, a Euclidean metric is computed as the accumulated square difference between the expected and actual sample values. The input sequence that generates the smallest Euclidean metric is the most likely sequence to have created the actual sample values; this sequence is therefore selected as the output of the sequence detector.
To facilitate the demodulation process, the sequence detector comprises path memories for storing each of the possible input sequences and a corresponding metric. A well known property of the sequence detector is that the paths storing the possible input sequences will "merge" into a most likely input sequence after a certain number of sample values are processed, as long as the input sequence is appropriately constrained. In fact, the maximum number of path memories needed equals the number of states in the trellis diagram; the most likely input sequence will always be represented by one of these paths, and these paths will eventually merge into one path (i.e., the most likely input sequence) after a certain number of sample values are processed.
The "merging" of path memories is understood from the trellis diagram of FIG. 2B where the "survivor" sequences are represented as solid lines. Notice that each state in the trellis diagram can be reached from one of two states; that is, there are two transition branches leading to each state. With each new sample value, the Viterbi algorithm recursively computes a new error metric and retains a single survivor sequence for each state corresponding to the minimum error metric. In other words, the Viterbi algorithm will select one of the two input branches into each state since only one of the branches will correspond to the minimum error metric, and the paths through the trellis corresponding to the branches not selected will merge into the paths that were selected. Eventually, all of the survivor sequences will merge into one path through the trellis which represents the most likely estimated data sequence to have generated the sample values as shown in FIG. 2B.
In some cases, if the input sequence is not appropriately constrained through the use of a channel code, the path memories will not merge into one survivor sequence. Consider the PR4 trellis shown in FIG. 2B; an input sequence of all zeros or all ones will prevent the paths from merging which leads to multiple possible survivor sequences output by the detector. Data sequences which prevent the path memories from merging are referred to as "quasi-catastrophic" data sequence since they result in quasi-catastrophic errors in the output sequence. In order to avoid quasi-catastrophic errors, a channel code is typically employed which codes out of the recorded data all sequences which can prevent the path memories from merging.
Even if the quasi-catastrophic data sequences are coded out of the input sequence, the sequence detector can still make an error in detecting the output sequence if enough destructive noise is present in the read signal. The possible output sequences are different from one another by a minimum Euclidean distance; a detection error typically occurs when the signal noise breaches this minimum distance between valid output sequences. FIGS. 3A-3D illustrate the sample error sequences associated with the dominant minimum distance error events for a PR4 sequence detector in NRZ, PR4, EPR4 and EEPR4 space, respectfully. In general, a higher order sequence detector will outperform a lower order sequence detector due to the number of data samples the error event affects. Consider, for example, the first error event in the NRZ space shown in FIG. 3A. This error event generates two noise samples which corrupt two data samples (two output bits) in the PR4 space of FIG. 3B, four noise samples in the EPR4 space of FIG. 3C, and four noise samples with two having increased magnitude in the EEPR4 space of FIG. 3D. This "spreading out" of the error event reduces the probability of a detection error.
A minimum distance error event can occur where the data sequences diverge from a particular state in the trellis and then remerge at a later state. In a perfect system, all of the minimum distance error events will occur with equal probability. However, because the channel equalizers correlate the noise in the signal samples, the minimum length, minimum distance error events are more likely to occur. Thus, the error events shown in FIGS. 3A-3D are the "dominant" minimum distance error events because they are shortest in length. The first error event (+ in NRZ), which is the shortest error event, is typically the most dominant; however, depending on the partial response polynomial employed, other error events may become the most dominant as the linear bit density increases.
An increase in performance can be achieved by employing a channel code to code out data sequences associated with the minimum distance error events (similar to coding out the quasi-catastrophic data sequences), and then to match the trellis sequence detector to this channel code. For example, the minimum distance error events shown in FIG. 3A can be coded out by removing the bit sequences consisting of (1,0,1) or (0,1,0) from the input sequence. The state machine of a PR4 sequence detector can then be matched to this code constraint by removing the inner branches shown in FIG. 2A. With these branches removed, the minimum distance of the sequence detector increases from dmin.sup.2 =2 to dmin.sup.2 =4 (with the signal samples normalized to +1, 0, -1).
The recording and reproduction of digital data through a disk storage medium can be modeled as a communication channel. Partial response signaling is particularly well suited to disk storage systems because they are bandpass channels in nature and therefore less equalization is required to match the overall response to a desired partial response polynomial. Referring to FIG. 1A, higher order partial response polynomials, such as EEPR4, are more closely matched to the channel's natural response than lower order polynomials, particularly at higher linear densities. Thus, in addition to spreading out the error samples as shown in FIG. 3, higher order partial response channels typically provide better performance since less equalization is required to match the channel's response to the desired partial response. However, the trade-off in performance is the cost of complexity; the number of states in the state machine increases by 2.sup.n+1 which means an exponential increase in complexity. A full EEPR4 state machine comprises sixteen states (n=3), as shown in FIG. 6, as compared to only four states in a PR4 state machine, as shown in FIG. 2A. The complexity of the EEPR4 state machine can be reduced by matching it to a run-length limited (RLL) d=1 constraint (which prevents consecutive NRZI one bits) as illustrated in FIG. 7. The states and branches shown as dashed lines are eliminated due to the RLL d=1 constraint, leaving only ten states.
Another advantage of matching the EEPR4 state machine to a RLL d=1 constraint is that it codes out the minimum distance error events associated with an EEPR4 sequence detector. However, at higher linear densities (user densities of 2.5 to 3 channel symbols per pulse-width at half maximum PW50) the error event (+00+) in NRZ, which is not coded out by the RLL d=1 constraint, becomes the most dominant error event. Therefore, coding out the minimum distance error events provides less benefit at higher linear densities. The applicant's have determined that a modified EEPR4 channel (MEEPR4) with a polynomial of EQU (1+D)(1-D.sup.3)
exhibits a frequency response wherein the error event (+00+) in NRZ is attenuated at higher linear densities. In addition, MEEPR4 increases the signal-to-noise ratio (SNR) because it requires less equalization to match the response of the recording channel to the MEEPR4 target.
The MEEPR4 d=1 channel has been studied previously in a paper by K. Shimoda et al. entitled "New Type (1,7) RLL Partial Response over 5 Gbit/in.sup.2 Areal Density," IEEE Transactions on Magnetics, Vol. 33, No. 5, September 1997. However, as described in that paper, the MEEPR4 d=1 channel cannot be implemented directly because a certain data sequence generates quasi-catastrophic errors, namely the data sequence ( . . . 1,1,0,0,0,0,1,1,0,0,0,0,1,1. . . ) and the inverse sequence collectively referred to as the (2,4,2) quasi-catastrophic data sequence.
There is, therefore, a need for a sampled amplitude read channel which codes out the (2,4,2) quasi-catastrophic data sequence, thereby enabling the application of an MEEPR4 d=1 sequence detector for detecting binary data recorded on a disk storage medium. A further object of the present invention is to code out certain minimum distance error events to further enhance the performance of the MEEPR4 d=1 sequence detector. Yet another object of the present invention is to implement an additional constraint, an RLL k constraint, which enables operation of the gain control and timing recovery circuits of the sampled amplitude read channel. Still another object of the present invention is to provide a channel code with a high code rate for implementing the above constraints.